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Ordering number : ENA0194A
LV24100LP
Overview
Bi-CMOS IC
FM and AM Tuner IC for Small Portable Equipment
The LV24100LP is an innovative FM/AM tuner IC that is capable of configuring an FM/AM radio with just one external component. Since all the FM/AM radio functions are incorporated into a compact VQLP package with dimensions of only 5mmx5mmx0.8mm, this IC can easily incorporate FM/AM tuner function into mobile phones, PDA, MP3 player and other small mobile sets where space is always at a premium.
Functions
* FM Tuner * AM Tuner * MPX stereo decoder * Tuning
Features
* No external components required except for an AM bar antenna. * No alignments necessary * Improved selectivity with low FMIF frequency (110kHz) * Built-in adjacent channel interference total reduction (no 114kHz, no 190kHz) * New tuning system * Very high sensitivity reception with low-noise mixer input circuit * Built-in low power standby mode eliminates the need for a power switch circuit. * Composite output for RDS applications * 3-wire bus interface (data, clock, and NR-W) featured * Digital AFC function provided * Soft muting and stereo blend functions (8-step software control) * Support for manual search, automatic search, and auto preset * Support for reception of worldwide bands (reception of all bands in Japan, Europe, and the US enabled by changes in the program.)
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
N2107 TI IM 20060801-S00001 No.A0194-1/18
LV24100LP
Specifications
Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Symbol VCC max VDD max Digital input voltage VIN1 max VIN2 max Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg Conditions Analog block supply voltage Digital block supply voltage Clock, Data, NR_W External_clk_in Ta70C, Mounted on a specified board * Ratings 5.0 4.5 VDD+0.3 VDD+0.3 140 -20 to +70 -40 to +125 Unit V V V V mW C C
Note: Mounted on a specified board: 40mmx50mmx0.8mm, glass epoxy Operating Condition at Ta = 25C
Parameter Recommended supply voltage Symbol VCC VDD Operating supply voltage range VCC op VDD op VIO op Interface voltage Conditions Analog block supply voltage Digital block supply voltage Ratings 3.0 3.0 3.0 to 4.8 3.0 to 4.0 1.8 to 4.0 Unit V V V V V
Note: The VIO application voltage must be either equivalent to VDD or the VDD value or less. (VIO VDD) Interface Block Allowable Operation Range at Ta = -20 to +70C, VIO = 3.0V, VSS = 0V
Parameter Supply voltage Digital block input Symbol VDD VIH VIL Digital block output IOL VOL Clock input operating frequency External clock operating frequency External clock operating voltage fclk fclk_ext Vclk_ext High level input voltage range Low level input voltage range Output current at Low level Output voltage at Low level IOL=2mA (Pin29) clock frequency for 3wire_bus (Pin31) clock frequency for external input (Pin31) clock voltage for external input 32k 0.7VDD Conditions min 2.5 0.7VDD 0 2.0 0.6 0.7 14M VDD Ratings typ max 4.0 VDD 0.6 V V V mA V MHz Hz V Unit
Note: External clock input (pin31) allows also input of the sine wave signal. Frequency deviation is need 250ppm.
No.A0194-2/18
LV24100LP
Operating Characteristics at Ta=25C, VCC=3.0V, VDD=3.0V, VIO=3.0V, VSS=0V, Soft Mute/Soft Stereo=off, with the specified test circuit. Output level setting means control register Block 2, Register 07h Bit 6(VOLSH)=0, Register 09h Bit 0 (nAUBST) =0.
Parameter Current drain (in operation) Symbol ICCA_FM ICCA_AM ICCD Current drain (in standby) ICCA_stb ICCD_stb FM receive band FM receiving characteristics MONO : fc=80MHz, fm=1kHz, 22.5kHz dev. VIN=60dBV, Audio filter=IHF_BPF 3dB sensitivity Practical sensitivity 1 Practical sensitivity 2 (Reference) Demodulator output Channel balance Signal-to-noise ratio Total harmonic distortion 1 (MONO) Total harmonic distortion 2 (MONO) Field intensity display level Mute attenuation -3dB LS QS1 QS2 VO CB S/N THD1 THD2 FS Mute-Att 22.5kHz dev. output standard, input -3dB. Input level with S/N=30dB Input level with S/N=26dB Pin11 output Pin11/pin12 output Pin11 output Pin11 output, 22.5kHz dev. Pin11 output, 75kHz dev. Input level at which FS3 changes to FS4 Pin 11 output 35 60 70 50 -2 48 5 10 1.25 70 0 58 0.4 1.3 1.5 3.0 49 110 2 11 16 dBV dBV V mV dB dB % % dBV dB F_range Conditions min Measurement at pin 23 with FM 60dBV monaural input of the analog section. Measurement at pin 23 with AM 80dBV input of the analog section. Measurement at pins 27 and 40 with FM 60dBV input in the digital block. Measurement at pin 23 in the standby mode of the analog block. Measurement at pins 27 and 40 in the standby mode of the digital block. In the PCB mounting conditions 76 11 9 0.1 Ratings typ 14 12 0.5 3 3 max 17 15 0.8 30 A 30 108 MHz mA Unit
FM receive characteristic STEREO characteristic : fc=80MHz, fm=1kHz, VIN60dBV, L+R=90% (67.5kHz dev.), Pilot=10% (7.5kHz dev.), Audio filter = IHF_BPF+15kHz_LPF Separation Total harmonic distortion (Main) AM receive characteristic : fc=1.2MHz, fm=1kHz, 30% mod, Audio filter = IHF_BPF Demodulation output 1 Demodulation output 2 Signal-to-noise ratio 1 Signal-to-noise ratio 2 Total harmonic distortion Field intensity display level VO1 VO2 S/N1 S/N2 THD FS VIN=30dBV, Pin11 output VIN=80dBV, Pin11 output VIN=30dBV, Pin11 output VIN=80dBV, Pin11 output VIN=80dBV, Pin11 output Input level at which FS3 changes to FS4 35 35 30 14 40 55 50 21 45 1.0 3.0 49 80 75 mVrms mVrms dB dB % dBV SEP THD-ST L-mod, Pin11/pin12 output Main-mod (for L+R input), Pin11 output 20 35 1.3 3.0 dB %
No.A0194-3/18
LV24100LP
Package Dimensions
unit : mm (typ) 3302A
Top View Bottom View
0.35 5.0 21 20 5.0 30 0.35 (0.7) 31
0.4
40 11 10 0.85MAX 0.2 1 (0.7)
0.05 0 NOM
SANYO : VQLP40(5.0X5.0)
Block Diagram and Pin Assigment
CLOCK
Vstabi
30
29
28
27 VDD
26
25
24
23 VCC
22
21
Vstabi2
DATA
NR_W
VDD
VCC
NC
NC
NC
CLK_IN 31 NC 32 Package-GND 33 Package-GND 34 Package-GND 35 Pre-scaler Package-GND 36 Package-GND 37 Package-GND 38 De-emphasis NC 39 Ant-cap. VI/O 40 GND 1 GND 2 AM-ANT1 3 AM-ANT2 4 FM-ANT1 5 FM-ANT2 GND 6 GND 7 NC 8 NC 9 NC 10 NC Buffer amp. Quadrature mixer Digital interface Quadrature oscillator Power management Tuning system Voltage stabilizer
20 19 18 17 16 Demodulator 15 Stereo decoder 14 13 12 11
MPX NC Package-GND Package-GND Package-GND Package-GND Package-GND Package-GND LINE-OUT-R LINE-OUT-L
Selectivity filter
Top view
No.A0194-4/18
LV24100LP
Pin Discription
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND AM-ANT1 AM-ANT2 FM-ANT1 FM-ANT2 GND NC NC NC NC LINE-OUT-L LINE-OUT-R Package-shield GND Package-shield GND Package-shield GND Package-shield GND Package-shield GND Package-shield GND NC MPX Vstabi2 NC VCC NC Vstabi. NC VDD NR_W DATA CLOCK CLK_IN NC Package-shield GND Package-shield GND Package-shield GND Package-shield GND Package-shield GND Package-shield GND NC VI/O Digital interface supply voltage GND for Package-shield GND for Package-shield GND for Package-shield GND for Package-shield GND for Package-shield GND for Package-shield I I/O I I Digital supply voltage Digital interface Read/Write Digital interface DATA Digital interface Clock Reference clock-source input for measurement Connect to GND if not used Stabilizer voltage 2.4V Analog supply voltage MPX-signal output 2nd Stabilizer voltage VCC-0.3V 3.0V O O Radio Lch Line-output Radio Rch Line-output GND for Package-shield GND for Package-shield GND for Package-shield GND for Package-shield GND for Package-shield GND for Package-shield 1.2V 1.2V I I I I Name I/O Description Analog and Digital GND AM Antenna input AM Antenna GND FM Antenna input FM Antenna GND Analog and Digital GND Remarks DC Voltage
No.A0194-5/18
LV24100LP
The PCB mounting conditions which cover FM receiving frequency range 76MHz to 108MHz This IC Package is printed inductor backside of the package for local oscillation. It is necessary to place GND pattern right under the IC package for covering received frequency range 76MHz to 108MHz. This IC is measured under this condition for received frequency range. Then, the GND pattern must be placed at the center of the IC. Printed circuit board
LV24100LP Side-A
Side-B GND pattern
GND pattern
LV24100LP Evaluation board side-A
PCB layout recommendations
5.0x5.0 1 0.7 0.8 5.0x5.0 3.4 1 0.8 0.2 0.8
2.2 PCB GND Layer Layer 0.4 X=3.4
21 0.35
0.8 21
Substrate layout of LV24100LP
PCB pattern light under of LV24100LP
At the GND pattern light under of LV24100LP, X=3.4mm is recommended. The limit of X is min=2.2mm and max=3.6mm same as GND shield size of LV24100LP. Please do not arrange other wirings as much as possible within 0.4mm under the GND pattern.
No.A0194-6/18
LV24100LP
Serial Data Timing
* Write timing
tW tHD tDL DATA tCL VIH VIL CLOCK
NR_W
tCH
Symbol tW tDL tHD tCH tCL Delay from command to data
Conditions min 750 750 750 750 750
Ratings typ max
Unit ns ns ns ns ns
Delay from data stable to data latch time Data Hold time Clock High-level time Clock Low-level time
* Read timing
tW NR_W tSU DATA tHD
CLOCK
Symbol tW tSU THD
Conditions min Delay from command to 1st data bit Data Setup time Data hold time 350
Ratings typ max
Unit ns 350 350 ns ns
No.A0194-7/18
LV24100LP
* External clock timing (Pin 31)
tCH CLK_IN VIH VIL
tCL
Symbol tCH tCL fext VIH VIL Clock High-level time Clock Low-level time External clock frequency High level input voltage level Low level input voltage level
Conditions min 36 36 32 0.7VDD 0
Ratings typ max 15625 15625 14000 VDD 0.6
Unit ns ns kHz V V
Digital Interface
* 3-wire bus (For communication line) Access to the LV24100 is done through the 3-wire bus.
CLOCK NR_W DATA Data strobe, input to the LV24100 Command (Read or write data), input to the LV24100 Bi-directional pin: Written data in to the LV24100 when NR_W is high, Read data from the LV24100 when NR_W is low.
The LV24100 can be configured to generate interrupt through the DATA-line. When interrupt mode is selected, care should be taken that the DATA-line connection to the application micro-controller also supports interrupt. When the required timing window for frequency measurements is not generated by the application micro-controller, an external clock must be connected to CLK_IN pin of the LV24100. * Register map The LV24100 registers are divided in 3 blocks:
Block 01h Block 02h Block 03h Status and measurement FM Control AM control
To access a register in a block, the block must be first selected by writing the block number to the BLK_SEL register. Block selection can be skipped for subsequent accesses to other registers in the same block.
No.A0194-8/18
LV24100LP
The mapping is as follows:
Block 01h Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 02h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 03h 01h 02h 03h 04h Register name CHIP_ID BLK_SEL MSRC_SEL FM_OSC SD_OSC IF_OSC CNT_CTRL NA IRQ_MSK FM_CAP CNT_L CNT_H CTRL_STAT RADIO_STAT IRQ_ID IRQ_OUT BLK_SEL RADIO_CTRL1 IF_CENTER AM_CAP IF_BW RADIO_CTRL2 RADIO_CTRL3 STEREO_CTRL AUDIO_CTRL1 AUDIO_CTRL2 PW_SCTRL BLK_SEL AM_ACAP AM_FE AM_CTRL Access R W W W W W W W W R R R R R W W W W W W W W W W W W W W W W Interrupt mask CAP bank control for RF-frequency Counter value low byte Counter value high byte Control status Radio station status Interrupt identify Set Interrupt on DATA-line Access register 01h of block 1 Radio control 1 IF Center Frequency All to be set to "0" IF Bandwidth Radio control 2 Radio control 3 Stereo control Audio control 1 Audio control 2 Power and soft control Access register 01h of block 1 AM antenna capacitor AM front end control AM control Chip identification Block Select Measure source select DAC control for FM-RF oscillator DAC control for stereo decoder oscillator DAC control for IF oscillator Counter control Operation
Not mentioned registers are not defined and should not be accessed.
No.A0194-9/18
LV24100LP
Register Description
Block x, Register 01h-BLK_SEL-Block Select Register(Write only)
7 6 5 4 BN[7:0] Bit 7-0: BN[7:0]: 8-bit block number. For LV24100, the following numbers are valid: 01h. 02h. 03h. Note: This register can be accessed from any block 3 2 1 0
Block 1, Register 00h-CHIP_ID-Chip Identify Register(Read only)
7 6 5 4 ID[7:0] Bit 7-0: ID[7:0]: 8-bit chip ID. For LV24100, value 7 should be read 3 2 1 0
Block 1, Register 02h-MSRC_SEL-Measurement Source Select Register(Write-only)
7 MSR_O Bit 7: 6 AFC_LVL 5 AFC_SPD 4 MSS_RF16 3 MSS_AM 2 MSS_SD 1 MSS_FM 0 MSS_IF
MSR_O: Output measure source to DATA-pin 0 = Measuring source not available at DATA-pin (normal operation). 1 = Measuring source available at DATA-pin (test mode).
Bit 6:
AFC_LVL: AFC trigger level 0 = AFC is always active (trigger at 0dBV) 1 = AFC is only active when field strength is above 20dBV
Bit 5:
AFC_SPD: AFC speed 0 = AFC adjusts with 3Hz speed 1 = AFC adjusts with 8kHz speed (test mode)
Bit 4:
MSS_RF16: RF/16 measurement. 0 = Disable RF/16 oscillator measurement 1 = Enable RF/16 oscillator measurement
Bit 3:
MSS_AM: AM antenna frequency measurement. 0 = Disable AM antenna measurement 1 = Enable AM antenna measurement
Bit 2:
MSS_SD: Stereo decoder oscillator measurement 0 = Disable stereo decoder oscillator measurement 1 = Enable stereo decoder oscillator measurement
Bit 1:
MSS_FM: FM RF oscillator measurement 0 Disable FM RF oscillator measurement 1 = Enable FM RF oscillator measurement
Bit 0:
MSS_IF: IF oscillator measurement 0 = Disable IF oscillator measurement 1 = Enable IF oscillator measurement
Note: Only one of the measurement source MSS_xx bits may be set at a time. The FM RF frequency is divided by 256 or 16 before it goes to the measuring circuitry.
Block 1, Register 03h-FM_OSC-FM RF Oscillator Register(Write-only)
7 6 5 4 FMOSC[7:0] Bit 7-0: FMOSC[7:0]: DAC value to control the FM RF oscillator (fine step) Note: Positive DAC control (i.e. the frequency increases with the register's value) See also FM_CAP register 3 2 1 0
Block 1, Register 04h-SD_OSC-Stereo Decoder Oscillator Register(Write-only)
7 6 5 4 SDOSC[7:0] Bit 7-0: SDOSC[7:0]: DAC value to control the stereo decoder oscillator Note: Positive DAC control(i.e. the frequency increases with the register's value) 3 2 1 0
No.A0194-10/18
LV24100LP
Block 1, Register 05h-IF_OSC-IF Oscillator Register(Write-only)
7 6 5 4 IFOSC[7:0] Bit 7-0: IFOSC[7:0]: DAC value to control the IF oscillator Note: Positive DAC control (i.e. the frequency increases with the register's value) 3 2 1 0
Block 1, Register 06h-CNT_CTRL-Counters Control Register(Write-only)
7 CNT1_CLR Bit 7: 6 CTAB2 0 = Normal mode 1 = Clear and keep counter 1 in reset mode Bit 6-4: CTAB[2:0]: Tab select for counter 2 measuring interval bits Value 000b 001b 010b 011b 100b 101b 110b 111b Bit 3: Dec. 0 1 2 3 4 5 6 7 Stop value Stop after 2 counts Stop after 8 counts Stop after 32 counts Stop after 128 counts Stop after 512 counts Stop after 2048 counts Stop after 8192 counts Stop after 32768 counts 5 CTAB1 4 CTAB0 3 SWP_CNT_L 2 CNT_EN 1 CNT_SEL 0 CNT_SET
CNT1_CLR: Clear counter 1 bit
SWP_CNT_L: Swap counter 1 and counter 2 bit(Active low) 0 = Clock source 1 to counter 2, clock source 2 to counter 1(swapping) 1 = Clock source 1 to counter 1, clock source 2 to counter 2(no swap)
Bit 2:
CNT_EN: Enable the currently selected counter bit 0 = Disable counter(stop counting) 1 = Enable counter(counting mode)
Bit 1:
CNT_SEL: counter select bit 0 = Select counter 1 for measurement 1 = Select counter 2 for measurement
Bit 0:
CNT_SET: Set counters bit 0 = Normal mode 1 = Set both counter 1 and counter 2 to FFFFh and keep them set
Block 1, Register 08h-IRQ_MSK-Interrupt Mask Register(Write-only)
7 Reserved Bit 7: Bit 6: 6 IM_MS 5 Reserved 4 3 IRQ_LVL 2 IM_AFC 1 IM_FS 0 IM_CNT2
Reserved: Must be programmed with 0. IM_MS: Mono/Stereo interrupt mask bit 0 = Disable mono/stereo change interrupt 1 = Enable mono/stereo change interrupt
Bit 5: Bit 4: Bit 3:
Reserved: Must be programmed with 0. Reserved: Must be programmed with 0. IRQ_LVL: Interrupt level select bit 0 = Drive DATA-line from low to high when interrupt occurs(active high) 1 = Drive DATA-line from high to low when interrupt occurs(active low)
Bit 2:
IM_AFC: AFC out of range interrupt mask bit 0 = Disable AFC out of range interrupt 1 = Enable AFC out of range interrupt
Bit 1:
IM_FS: Field strength change interrupt mask bit 0 = Disable field strength change interrupt 1 = Enable field strength change interrupt
Bit 0:
IM_CNT2: Counter 2 counting done interrupt mask bit 0 = Disable counter 2 counting done interrupt 1 = Enable counter 2 counting done interrupt
No.A0194-11/18
LV24100LP
Block 1, Register 09h-FM_CAP-FM RF Capacitor Bank Register(Write-only)
7 6 5 4 FMCAP[7:0] Bit 7-0: FMCAP[7:0]: CAP bank value to control the FM RF frequency (coarse steps) Note: 71/2 bit CAP value (Bit[7:6]: Combination 10b and 01b results in the same CAP-range) Negative control: de RF frequency decreases when increasing the register's value See also FM_OSC register 3 2 1 0
Block 1, Register 0Ah-CNT_L-Counter Value Low Register(Read-only)
7 6 5 4 CNT_LSB[7:0] Bit 7-0: CNT_LSB[7:0]: Lower 8-bit value of the 16 bit counter 3 2 1 0
Block 1, Register 0Bh-CNT_H-Counter Value High Register(Read-only)
7 6 5 4 CNT_MSB[7:0] Bit 7-0: CNT_MSB[7:0]: Upper 8-bit value of the 16 bit counter 3 2 1 0
Block 1, Register 0Ch-CTRL_STAT-Control Status Register(Read-only)
7 REV3 Bit 7-4: Bit 3-2: Bit 1: 6 REV2 5 REV1 4 REV0 3 Reserved 2 1 COV_FLG 0 AFC_FLG
REV[3:0]: should be read as 0Dh Reserved[1:0]: should be read as all 1 COV_FLG: counter overflow flag 0 = No overflow of the internal counter 1 = The last counting loop causes overflow of the internal counter
Bit 0:
AFC_FLG: AFC out of range bit 0 = AFC is within control range 1 = AFC is out of control range
Note: Reading this register will clear AFC, count 2 done interrupt. COV_FLG is clear when CLR_CNT1 bit of CNT_CTRL register is high
Block 1, Register 0Dh-RADIO_STAT-Radio Station Status Register(Read-only)
7 RSS_MS Bit 7: RSS_MS: Radio station mono/stereo state bit 0 = Mono 1 = Stereo Bit 6-0: RSS_FS[6:0]: Radio station field strength bits 1111111b = Field strength less then 10dBV 0111111b = Field strength between 10 to 20dBV 0011111b = Field strength between 20 to 30dBV 0001111b = Field strength between 30 to 40dBV 0000111b = Field strength between 40 to 50dBV 0000011b = Field strength between 50 to 60dBV 0000001b = Field strength between 60 to 70dBV 0000000b = Field strength above 70dBV Note: Reading this register will clear field strength and mono/stereo interrupt 6 5 4 3 RSS_FS 2 1 0
No.A0194-12/18
LV24100LP
Block 1, Register 0Eh-IRQ_ID-Interrupt Identify Register(Read-only)
7 Reserved Bit 7: Bit 6: Bit 5: 6 5 II_CNT2 4 Reserved 3 II_AFC 2 Reserved 1 0 II_FS_MS
Reserved: should be read as 1 Reserved: should be read as 1 II_CNT2: Counter 2 counting done flag 0 = No counting 2 counting done interrupt 1 = Measuring with counter 2 is done
Bit 4: Bit 3:
Reserved: should be read as 0 II_AFC: AFC out of range interrupt bit 0 = No AFC interrupt 1 = AFC fails to hold the RF-frequency in range
Bit 2: Bit 1: Bit 0:
Reserved: should be read as 0 Reserved: should be read as 0 II_FS_MS: Field strength and Mono/stereo interrupt bit 0 = No change in either the field strength or the mono/stereo mode 1 = Change in field strength bits detected or mono/stereo mode has changed
Block 1, Register 0Fh-IRQ_OUT-Set Interrupt Out Register(Write Only)
7 6 5 4 IRQO_VAL[7:0] Bit 7-0: IRQO_VAL[7:0]: Write any value to this register will select the interrupt as output on the DATA-line of the LV24100 (the DATA-line can then be used as interrupt pin) 3 2 1 0
Block 2, Register 02h-RADIO_CTRL1-Radio Control 1 Register(Write-only)
7 EN_MEAS Bit 7: 6 EN_AFC 5 Reserved 4 AM_CD2 3 DIR_AFC 2 RST_AFC 1 AM_CD1 0 AM_CD0
EN_MEAS: Enable measurement bit 0 = Normal mode 1 = Measurement mode
Bit 6:
EN_AFC: Enable AFC bit 0 = Disable AFC 1 = Enable AFC
Bit 5:
EN_RF16:Enable RF16 Divider bit 0 = Disable RF16 1 = Enable RF16
Bit 4: Bit 3:
AM_CD2: AM clock divider bit 2. Should be kept at 1 in FM mode DIR_AFC: AFC direction bit 0 = AFC normal direction 1 = AFC reverse direction (for test purpose)
Bit 2:
RST_AFC: Reset AFC bit 0 = Normal operation 1 = Reset AFC to the middle of the control range
Bit 1: Bit 0:
AM_CD1: AM clock divider bit 1. Should be kept at 1 in FM mode AM_CD0: AM clock divider bit 0. Should be kept at 1 in FM mode
Note: The AM_CD[2:0] bits are used to scale the FM-RF frequency down to AM-RF frequency. In FM mode, the AM divider should be turned off. AM_CD[2:0] 0 1 2 3 4 5 6 7 Divider factor 48 64 80 96 128 160 192 Divider OFF Approx. AM-RF (in kHz) 1354 1015 812 677 507 406 338 2291 1718 1375 1145 859 687 572
Block 2, Register 03h-IFCEN_OSC-IF Center Frequency Oscillator Register(Write-only)
7 6 5 4 IFCOSC[7:0] Bit 7-0: IFCENT[7:0]: value for centering the IF frequency 3 2 1 0
No.A0194-13/18
LV24100LP
Block 2, Register 04h-AM_CAP(Write-only)
7 6 5 4 AM_CAP[7:0] Bit 7-0: AM_CAP[7:0]:all bit to be set to 0 3 2 1 0
Block 2, Register 05h-IF_BW-IF Bandwidth Register(Write-only)
7 6 5 4 IFBW[7:0] Bit 7-0: IFBW[7:0]: Value for IF bandwidth 3 2 1 0
Block 2, Register 06h-RADIO_CTRL2-Radio Control 2 Register(Write-only)
7 VREF2 Bit 7: 6 VREF 5 STABI_BP 4 IF_PM_L 3 DCFB_SPD 2 DCFB_OFF 1 AGCSP 0 Reserved
VREF2: VREF2 control bit 0 = VREF2 is ON 1 = VREF2 is OFF VREF: VREF control bit 0 = VREF is ON 1 = VREF is OFF
Bit 6:
Bit 5:
STABI_BP: Voltage stabilizer bypass bit 0 = Internal voltage is Vstabi (normal operation) 1 = Internal voltage is VCC (stabilizer bypassed)
Bit 4:
IF_PM_L: IF PLL mute bit 0 = IF PLL mute on (presetting IF mode) 1 = IF PLL mute off (normal operation mode)
Bit 3:
DCFB_SPD: DC feedback speed 0 = normal speed 1 = high speed (test mode)
Bit 2:
DCFB_OFF: DC feedback control 0 = Enable DC feedback (FM mode) 1 = Turn off the DC feedback (AM mode)
Bit 1:
AGCSP: AGC speed control bit 0 = Normal speed 1 = High speed (test mode)
Bit 0:
Reserved: should be written with 0
Block 2, Register 07h-RADIO_CTRL3-Radio Control 3 Register(Write-only)
7 AGC_SLVL Bit 7: Bit 6: 6 VOLSH 5 Reserved 4 AMUTE_L 3 SE_FM 2 SE_AM 1 Reserved 0
AGC_SLVL: AGC set level bit This bit must be set to 1 VOLSH: Volume level shift bit 0 = Normal volume level 1 = Extra volume of 12dB
Bit 5: Bit 4:
Reserved: should be written with 0 AMUTE_L: Audio mute bit 0 = Audio muted 1 = Audio not muted
Bit 3:
SE_FM: FM radio select bit 0 = Disable FM radio 1 = Enable FM radio
Bit 2:
SE_AM: AM radio select bit 0 = Disable AM radio 1 = Enable AM radio
Bit 1: Bit 0:
Reserved: should be written with 0 Reserved: should be written with 0
Note: Do not set bit 3 and 2 on at the same time.
No.A0194-14/18
LV24100LP
Block 2, Register 08h-STEREO_CTRL-Stereo Control Register(Write-only)
7 FRCST Bit 7: 6 5 FMCS[2:0] FRCST: Force stereo bit 0 = Normal mode 1 = Force stereo mode for test Bit 6-4: Bit 3: FMCS[2:0]: FM channel separation bits 0...7=FM channel separation level DLT_TNE: Delta tune bit 0 = Decrease delta tune 1 = Normal delta tune Bit 2: PILOTCANC: Pilot cancellation bit 0 = No pilot cancellation 1 = Pilot cancellation enabled Bit 1: SD_PM: Stereo decoder PLL mute bit 0 = Stereo decoder PLL not muted(normal operation) 1 = Stereo decoder PLL is muted(presetting mode) Bit 0: ST_M: FM stereo/mono mode bit 0 = Stereo mode 1 = Mono mode 4 3 DLT_TNE 2 PILOTCANC 1 SD_PM 0 ST_M
Block 2, Register 09h-AUDIO_CTRL1-Audio Control 1 Register(Write-only)
7 6 5 4 Reserved Bit 7-1: Bit 0: Reserved: should be written with 0 nAUBST: Audio output level boost bit 0 = Boost output level with 3dB 1 = No output level boosting 3 2 1 0 nAUBST
Block 2, Register 0Ah-AUDIO_CTRL2-Audio Control 2 Register(Write-only)
7 Reserved Bit 7-6: Bit 5: 6 5 DEEMP 4 3 2 Reserved 1 0
Reserved: should be written with 1 DEEMP: De-emphasis bit 0 = De-emphasis 50s. 1 = De-emphasis 75s.
Bit 4-0:
Reserved: should be written with 0
Block 2, Register 0Bh-PW_SCTRL-Power and Soft Control Register(Write-only)
7 6 SS_CTRL Bit 7-5: SS_CTRL: Soft stereo control bits(8 levels) 000b = Minimal soft stereo(off) 111b = Maximal soft stereo level Bit 4-2: SM_CTRL: Soft audio mute bits(8 levels) 000b = Minimal soft audio mute(off) 111b = Maximal soft audio mute level Bit 1: Bit 0: Reserved: should be written with 0 PW_RAD: Radio circuitry power bit 0 = Radio circuitry is switched OFF. 1 = Switch radio circuitry ON Note: PW_RAD is 0 at power up 5 4 3 SM_CTRL 2 1 Reserved 0 PW_RAD
Block 3, Register 02h-AM_ACAP-AM Antenna Capacitor Bank Register(Write-only)
7 6 5 4 AMCAP[7:0] Bit 7-0: AMCAP[7:0]: CAP bank value to control the AM antenna frequency Note: AM antenna capacitor bank is controlled by 10 bits. The upper 2 bits are located in AM_FE register. Negative control: de frequency decreases when increasing the register's value. 3 2 1 0
No.A0194-15/18
LV24100LP
Block 3, Register 03h-AM_FE-AM Front End Register(Write-only)
7 6 AGC_LVL Bit 7-5: Bit 4: Bit 3-2: Bit 1-0: AGC_LVL[2:0]: AGC level bits AAGC_EG: AM AGC extra gain AAGC_GAIN[1:0]: AM AGC gain setting AMCAP[9:8]: Upper bits of AM antenna capacitor bank 5 4 3 AGC_GAIN 2 1 AMCAP9 0 AMCAP8
Block 3, Register 04h-AM_CTRL-AM Control Register(Write-only)
7 AMFE_AT Bit 7: 6 AABSW 5 nFIFAGC 4 AMFE_EN 3 AM_CAL 2 nAMEMG 1 FE_SPD[1:0] 0
AMFE_AT: AM front end attenuator 0 = Disable AM front end attenuator 1 = Enable AM front end attenuator
Note: This bit is don't care for FM and should be 1 for AM Bit 6: AABSW: AM antenna band switch 0 = Switch off AM antenna band 1 = Switch on AM antenna band Bit 5: nFIFAGC: Fast IF AGC(active low) 0 = Fast IF AGC speed 1 = Norma lF AGC speed Note: This bit must be 0 for FM. In AM mode, this bit must be 1 and can be changed to 0 during scanning for AM stations to speed up the scan operation. Bit 4: AMFE_EN: Enable AM front end bit 0 = Disable AM front end 1 = Enable AM front end Bit 3: AM_CAL: AM calibration bit 0 = Disable AM calibration(normal operation) 1 = Enable AM calibration(calibrate AM antenna frequency mode) Note: This bit must be set to 1 before measuring the AM antenna frequency Bit 2: nAMEMG: Extra gain AM mixer bit 0 = Extra mixer gain(normal operation) 1 = No extra mixer gain Bit 1-0: FE_SPD[1:0]: AM front end speed bits
No.A0194-16/18
LV24100LP
Test Circuit
Micro-controller 200 200 200 200
100nF 100nF
CLOCK
VDD(3.0V) VCC(3.0V) 22F
NR_W
DATA
VDD
VCC
1F
30 29 28 27 26 25 24 23 22 21 31 CLK_IN 32 33 34 35 36 37 38 39 40 VI/O 1 2 3 4 5 6 7 8 9 10 20 19 18 17
LV24100LP
16 15 14 13 12 11 100nF 100nF Line-out-R Line-out -L
10nF
180H
50 AM SSG 50 18H
1nF
50 FM SSG 50
No.A0194-17/18
LV24100LP
Application Circuit
Micro-controller 200 200 200 200 VDD
VCC(3.3V)
10 or 1H 0.22F 0.1F 22F 4.7 or 2.2H
Option
CLOCK
NR_W
DATA
VDD
VCC
1F
30 29 28 27 26 25 24 23 22 21 31 CLK_IN 32 33 34 35 36 GND* 37 38 39 40 VI/O 1 2 3 4 5 6 7 8 9 10 20 19 18 17
LV24100LP
16 15 14 13 12 11 1F 1F GND* Line-out-R
VCC
22F
1H 1H
Headphone Amp. Line-out -L 22F
2.2H
AM ANT 240H
GND* : Package shield GND
GND FM ANT 100pF
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above.
This catalog provides information as of November, 2007. Specifications and information herein are subject to change without notice.
PS No.A0194-18/18

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